Regarding the Future Outlook of CXL – Eugene Investment & Securities

This report is an English translation of Eugene Investment & Securities’ “CXL and Semiconductor Materials, Components, and Equipment” report.

Glossary:

• CXL: A type of computing interface—a standard interface designed to enable more efficient utilization of connections among the CPU, GPU, memory, etc.

• Interface: The point or boundary where two different systems or devices exchange information or signals; a system that helps users operate devices easily.

• PCIe: A standard interface for connecting internal computer components. It is primarily used for high-speed components such as GPUs, SSDs, Ethernet cards, and RAID cards. Evolved from the traditional PCI bus standard, it offers data transfer speeds more than twice as fast, and it was established by PCI-SIG under Intel’s leadership.

• Communication Protocol: A set of rules required for computers to connect and exchange information smoothly while minimizing errors (essentially the same as a protocol).

• Warm Data: A type of data that does not fall under hot data or cold data, and is accessed frequently only for a certain period.

• Fabric Network: An architecture where devices are interconnected, primarily used in data center network architectures.

• PHY: Refers to the physical layer in computer networks, the layer that implements the fundamental hardware transmission technologies.

• ACF (Accelerated Compute Fabric): A structure aimed at enhancing performance by consolidating multiple network layers within a device.

• Von Neumann Architecture: The most widely used computer architecture, consisting of a CPU, memory, and programs.
Introduction to CXL

What is CXL?

CXL, Compute Express Link

Connect and Compute Rapidly

• It is a next-generation interface designed to efficiently bundle computing systems for rapid computation. Previously, it was challenging to interconnect GPUs, CPUs, memory, and storage due to the differing interfaces; CXL consolidates these previously separate interfaces into one.

• CXL integrates multiple interfaces and communication protocols (based on PCIe) that were once divided.

• The reasons for this consolidation are twofold: 1) to enhance system computation speed and data processing speed, and 2) to meet the growing demand for more efficient memory utilization.

• Simple Analogy: Imagine the CPU, GPU, and DRAM each drinking water from their own cup. When the available water is insufficient, they end up frequently communicating with each other—asking, “Give me this much, take that much”—which creates a dilemma. With the introduction of a central unit called the CXL controller, they can now quickly draw as much water as needed from one huge water container.

• Additionally, in the past, virtual memory technology was used to address insufficient memory capacity. However, this approach came with risks such as slower speeds and an increased possibility of errors, because infrequently used data was moved from memory to secondary storage and then retrieved back into memory when needed, resulting in slower performance.

CXL Memory Pooling Architecture

Source: ETRI, Eugene Investment & Securities

An Idea Launched for Scalability and Speed

• CXL originates from the need to place warm data—data that lies between hot and cold—into a large-scale, intermediate repository.

• When handling ambiguous data, it offers relatively lower bandwidth compared to DRAM dedicated solely for CPUs or GPUs.

• Utilizing a CXL structure in devices with insufficient memory enables memory expansion without the need for a server replacement.

• By supporting high-bandwidth connections, it efficiently increases the amount of data that can be handled at one time.

• Simple Analogy: The CXL controller determines the necessary amount of water and distributes it effectively, creating the effect of an increased water supply. Instead of exchanging small quantities of water, it allows drawing from a large container, thereby increasing the total amount that can be handled.

From a CPU-Centric to a Memory-Centric Computing Architecture

Data: SK Hynix, Eugene Investment & Securities

CXL Consortium

• Formed in 2019 by the x86 technology camp led by Intel, it initially included 15 board member companies such as Samsung Electronics, Nvidia, and Microsoft, and has since expanded to over 240 companies.

• Although adhering to the CXL specification itself is not particularly challenging—making it a market that various companies can easily enter—the competitive edge lies in how each company leverages the standard to secure customers and commercialize products with satisfactory specifications.

• While HBM is a performance-first product that focuses on increasing bandwidth, CXL takes a different approach by reducing bandwidth in favor of sharing memory. This increases overall capacity and prioritizes inter-chip connectivity and cost-effectiveness. Consequently, some believe that CXL may not be ideally suited for AI training and workloads that demand extremely high-end technology.

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CXL Technical Architecture

By Protocol, Device, and Version

Types of CXL Protocols

CXL.io, CXL.memory, and CXL.cache

• Protocol: A set of rules that computers or network devices follow when communicating with each other. It is a compatibility-focused system that defines the data format, error handling methods, and signaling schemes used to transmit data in a common language.

• The main sub-protocols of CXL consist of three types: .io, .cache, and .mem.

• Simple Explanation: When connected to a CXL host, discovery, enumeration, configuration, and management are performed via CXL.io. CXL.cache enables CXL devices to access the processor’s cache memory, while CXL.mem allows the processor to access the CXL device’s memory. Among these, the .cache and .mem protocol stacks are optimized for low latency.

CXL Protocol Structur

Types of CXL Devices

Devices are classified into three types based on combinations of CXL protocols:

• Type 1 CXL Device:

A device that maintains cache coherence with the host (CPU)’s cache memory but does not include any host-managed memory.

Example: NIC (Network Interface Card), accelerators (devices without host-managed memory).

• Type 2 CXL Device:

A device that uses all three sub-protocols (.io, .cache, .mem) to maintain full cache coherence with the host (CPU) and also includes host-managed device memory. This type is useful for more complex computational tasks due to its wide bandwidth.

Example: GPU cards or FPGA boards with built-in memory such as HBM.

• Type 3 CXL Device:

A device that supports the .io and .mem sub-protocols and consists solely of memory managed by the host. Increasing memory capacity and bandwidth with this type requires adding memory channels, which increases engineering complexity and cost. However, Type 3 devices allow for flexible expansion of capacity and bandwidth without increasing the number of CPU memory channels.

Example: Memory expansion devices composed of DRAM or NAND.

Types of CXL Versions

Three CXL versions have been introduced to date.

• Starting with Version 1.0:

Proposed by Intel in 2019, followed by the release of versions 1.1, 2.0, and 3.0.

• CXL 1.0, 1.1:

These versions are designed to meet the demand for flexible interconnection among heterogeneous resources and for increased memory capacity and bandwidth. They add coherence maintenance mechanisms and memory semantic access mechanisms to the functionality of PCIe 5.0. They originated as a 1:1 connection standard between a host (CPU) and a single device.

• CXL 2.0:

This version provides a mechanism for multiple computing nodes to access pooled resources via a CXL switch. It eliminates the need for a single computing node to be excessively equipped with memory or accelerators, allowing for flexible responses to temporary demand surges. CXL 2.0 efficiently resolves memory overprovisioning issues and significantly reduces the TCO (Total Cost of Ownership) — marking the first support for memory pooling.

• CXL 3.0:

Based on PCIe 6.0, CXL 3.0 introduces a PAM4 signaling mechanism that doubles the communication bandwidth compared to previous versions while simultaneously optimizing communication latency.

CXL Versions: CXL 3.1 Released

• In November 2023, with the release of CXL 3.1, a new fabric architecture was introduced. While CXL 3.0 provided a multipath architecture distinct from earlier versions, CXL 3.1 unveiled a CXL Fabric Manager API for PBR (Port Based Routing) switches, supporting a wider range of architectures compared to the previous HBR (Hierarchy Based Routing).

• The concept of GIM (Global Integrated Memory) was introduced to allow the sharing of local memory among hosts (CPUs). Although this structure enables remote hosts or devices to access the GIM, it is not intended for caching or memory pooling purposes; therefore, the use of .cache and .mem protocols is restricted.

• Additionally, virtualization-based security protocols are supported and memory expansion devices have been improved, reinforcing its position as the next-generation memory interconnect.

• However, since devices utilizing CXL 1.1 and 2.0 have only just been released, further developments need to be closely monitored.

Below this section, we cover the outlook of the CXL market and related companies.